1. Technical Field
The disclosed subject matter relates generally to implantable medical devices and more particularly to reconfigurable non-volatile programming in an implantable medical device.
2. Background Information
Various diseases and disorders of the nervous system are associated with abnormal neural discharge patterns. One treatment regimen for such diseases and disorders includes drug therapy. Another treatment technique includes the implantation in the patient of an implantable medical device that comprises a pulse generator for electrically stimulating a target location of the patient's neural tissue. In one such available treatment for epilepsy, the vagus nerve is electrically stimulated by a neurostimulator device substantially as described in one or more of U.S. Pat. Nos. 4,702,254, 4,867,164, and 5,025,807, all of which are incorporated herein by reference.
Some implantable pulse generators used for electrical stimulation of neurological tissue operate according to a therapy algorithm programmed into the device by a health care provider such as a physician. One or more therapy parameters or the actual software running on the device may thereafter be changed by reprogramming the neurostimulator after implantation by transcutaneous communication between an external programming device and the implanted neurostimulator. The ability to program (and later re-program) the implanted medical device (“IMD”) permits a health care provider to customize the therapy provided by the implanted device to the patient's needs, to update the therapy periodically should those needs change, and to update the software of the device, including the operating system.
Various reprogrammable IMDs such as those discussed above are processor-controlled. The processors in such devices execute software loaded into memory contained within the IMD. For program security, various IMDs in the related art use read-only memory (“ROM”) or programmable read-only memory (“PROM”). Use of ROM or PROM ensures the security of the programming stored therein. However, when software improvements arise, there is a need for upgrades or modifications to the software stored in the IMD, and ROM and PROM memories have the inherent limitation that they cannot be reprogrammed without physically changing the memory in the IMD, thus necessitating an explant of the IMD.
For these reasons, many IMDs of the related art use re-writable memory (i.e. random-access memory, or “RAM”) that enables upgrades and modification to the software, in combination with some form of ROM. Each of the methods currently used in the related art has limitations, as discussed below.
Various IMDs employ volatile RAM, wherein program contents are volatile and subject to loss due to power fluctuations. One limitation of such a design is that loss of power results in an unrecoverable loss of the programming and the therapy parameters stored therein. A further shortcoming of such a design is that when a software program is executed directly from RAM (i.e., without employing virtual memory, pointers and the like), error checking is required for all instructions prior to every execution to prevent execution of an instruction altered by a power fluctuation. The requirement of error checking circuitry adds significant complexity to the IMD system.
Other IMDs of the related art use volatile, programmable RAM for the main program with a program back-up in ROM, wherein program contents in RAM may be lost due to power fluctuations, but upon losing power, the IMD reverts to the non-modifiable back-up program in stored in ROM. One limitation of such a design is the requirement of both a RAM and a ROM of sufficient size to store the executable program. Various designs in the related art have attempted to address this limitation. For example, in one design, the majority of the executable program may be stored in ROM while pointers to the various tasks in ROM are maintained in RAM, backed by Electrically Erasable Programmable Read Only Memory (EEPROM). While such a design minimizes the size of the RAM needed, such an approach also limits the degree of possible upgrade or modification based on the quantity of available RAM and the granularity of the tasks (i.e. the size of individual tasks relative to the code size and execution time). Another related design provides RAM and ROM of similar sizes, and uses a memory mapping system to swap either type of memory into a virtual memory space used by the processor. Such a design does not solve the problem that both the RAM and the ROM must be of sufficient size to store the executable program and the processor cannot directly execute the program. Additionally, a virtual memory design adds undesirable complexity to the IMD.
Various other IMDs employ volatile, programmable RAM backed up by program back-up in non-volatile Ferroelectric RAM (“FRAM”). One limitation of such a design is that both the RAM and the FRAM must be of sufficient size to store the executable program. Also, FRAM suffers from the deficiency that repeated read access of a FRAM location causes the FRAM to lose its non-volatility. Specifically, the physical nature of the crystal employed by FRAM is such that an almost infinite number of writes is possible, but the crystal deteriorates with each read, causing the FRAM to lose its non-volatility after a number of reads (typically in the range of 10 billion reads). The limited non-volatility lifetime of FRAM is particularly problematic for executable programs stored in the FRAM. Such programs often contain execution loops that result in repeated access of the FRAM. For applications such as the execution of software in an IMD, wherein relatively few writes are necessary, but, taking programming loops into account, vast numbers of reads are necessary, FRAM is thus inadequate. Still further, when the program is executed directly from RAM, there is a need for error checking on all instructions prior to execution to prevent execution of an instruction altered by a power fluctuation, adding significant complexity to the IMD system.
Still other IMDs of the related art use volatile, programmable RAM with a program back-up in a Serial Electrically Erasable Programmable ROM (“SEEPROM”). Such a design requires both RAM and SEEPROM of sufficient size to store the executable program. A further shortcoming of such a design is that when programming is executed directly from the RAM, as before, error checking is required for all instructions prior to execution to prevent execution of an instruction altered by a power fluctuation.
It is desirable, therefore, for an IMD, such as a neurostimulator, to be able to upgrade both therapy parameters and operational programming for the device post-manufacture and/or post-implant without the need for 1) large amounts of RAM, 2) ROM or RAM back-up, 3) indirect execution, (e.g., with a virtual memory area, pointers or the like) or 4) instruction error-checking.